Orthogonal frequency-division multiplexing (OFDM) is a method of encoding digital data on multiple carrier frequencies. In recent years, OFDM has developed into an increasingly popular scheme for digital communication, for both wireless and wired communications. OFDM modulation may use an Inverse Fast Fourier Transform (IFFT) as a way for generating the multiple carrier waveform. The IFFT operation is typically performed as a single, monolithic operation, resulting in what is frequently referred to as OFDM symbols. An OFDM symbol comprises an RF signal time slice that represents an integer number of bits. In a transmission context, a symbol is placed on a transmission channel at one or more predetermined symbol rates, and the receiving device detects the sequence of symbols on the channel in order to reconstruct the transmitted data. OFDM data symbols are converted by an FFT in a receiver into a plurality of frequency bins or carriers of a given bandwidth, together representing a transmission symbol. Many processing operations are constrained by the data set size of a symbol
Over time, OFDM methods have been using an ever increasing (I)FFT symbol size. As the symbol size increases, memory requirements for the (I)FFT and various pre-processing steps have increased proportionally, making, for example, field-programmable gate arrays (FPGAs) or very large scale integration (VLSI) chips such as application specific integrated circuits (ASICs) that are used in the process more complicated and costly. The increase in cost is related to many factors, one of which is an increase in the physical chip area that is required to implement a processing function and to accommodate the additional memory used in the processing function. Memory occupies significant portions of the physical area of such chips, as a result of which memory is a significant factor in chip cost. The added memory also adds to an increase in power consumption, which impacts not only power supply design considerations but also cooling requirements.
In the known system, a minimum amount of memory (e.g., random access memory (RAM)) is required to perform each processing function of the multiple processing functions performed in an OFDM transmitter, as well as to perform the corresponding inverse processing functions in an OFDM receiver. Typically, each processing operation is designed and performed independently (e.g., at the most local level) of other processing functions with the output of the processing operation being data that is the result of the completed function. To accomplish the independent operation of the processes, each processing operation includes its own memory block that is used to perform its configured function. As the number of processing steps (e.g., blocks) in the system increases, the total amount of memory required for the system increases linearly because each processing step stores its data in its own memory space. Known methods implement and complete each processing operation independently, thereby reducing the design complexity for the system but resulting in each processing step requiring its own memory.
FIG. 1 illustrates a generic prior art processing block 100, which may be used in the context of a system that includes a number of such processing blocks connected in series. Each processing block 100 receives data at an input, performs its respective function on the incoming data, and outputs data that has been modified according to the function. The output data may be provided to a further processing block or to another element of the system. In an example of the prior art processing block, the incoming data includes a string of data values that are each assigned an address. The addresses are used to write the data values into corresponding address spaces in a memory 102. The addresses assigned to the data values are not in sequential order but instead are non-sequential addresses according to the function to be performed by the processor block 100. The addresses may be referred to as non-sequential write addresses. The data (e.g., D0, D1, D2, . . . DN−1) is written into the memory 102 using the non-sequential write addresses. As a result, the data values are stored in the memory 102 in a non-sequential order. The stored data values are then read from the memory 102 using sequential read addresses to obtain the data values in the order in which they are stored in the memory. As a result, the data values which have been output from the memory 102 in this way are formatted as if the function of the processing block 100 has been performed directly on the data. The resulting processed data is output from the processing block 100.
In a particular example, the processing operation for the processing block 100 is accomplished by modifying the data, e.g., including but not limited to reordering the data values as they are stored into the memory 102 according to the addresses generated by a non-sequential address generator 104 that is internal to the processing block 100. After the data has been stored in the memory 102 as reordered or otherwise modified data, it is read from memory 102 according to a sequential address signal generated by a sequential read address generator 106 that is internal to processing block 100. The data is manipulated as it is written into memory 102 and the thus manipulated data is read out of the memory in the modified order or form. It will be understood that the particular manipulation of the data is based on the required function to be performed.
The processing blocks are typically designed as stand-alone processes by the circuit designers. Each is considered a black box from a design standpoint so that processing block may be added to a system independently of other system elements. FIG. 2 illustrates a plurality of processing blocks 202, 204, 206 and 208 coupled in series, where each processing block receives data, applies addresses to the data values, writes the data values into a memory according to the write addresses, reads the stored data from the memory according to read addresses, and outputs processed data. Thus each processing block 202-208 has its own memory to perform its function. The processing blocks 202-208 receive at their inputs only the data string of data values and output at their outputs only the data string of data values modified according to the respective function. For purposes of this discussion, it will be assumed that each processing block (e.g., 202, 204, 206, and 208) has a configuration similar to that of processing block 100 of FIG. 1.
Each processing block may perform a different function, such as frequency interleaving (e.g., processing block 202), pilot insertion (e.g., processing block 204), cell mapping (e.g., processing block 206) and FFT reordering (e.g., processing block 208). Since each block is independent of other blocks, the memory (e.g., random access memory (RAM)) requirement of the system 200 scales with the number of processing blocks. For example, for an FFT of size N, each processing block requires RAM of size N symbols. For N=32768 and 32 bit symbols, each RAM must be 32768×32 bits=1 Mbit. For four processing stages the system requires 4Mb of RAM.
Each memory block occupies a significant area on the semiconductor material of a processing chip and uses a significant portion of the power required by the chip. The cost of the processing chip depends to a great extent on the area occupied by the circuit elements. As memory requirements increase, the size, cost, and power requirements increase, which also increases the heat dissipation requirements. Combining some or all of the processing blocks into a single chip requires that significant areas of the chip are dedicated to the memory for the respective processing blocks, with a corresponding higher cost, higher power usage, and higher heat generation.
Since the data is manipulated by each processing block, each processing block includes its own memory, thereby requiring a linearly increasing amount of memory with each processing block. Accordingly, it would be beneficial to have a system and method that reduces the overall implementation cost, power consumption, complexity, and chip real estate of prior art signal processing systems